The present invention generally relates to digital clock signal generators and, more particularly, to a system and corresponding method of generating multiple clock phases within a single clock period of an input signal.
Multi-phase devices are used in connection with any group or series of devices that operate at different frequencies. For example, many application specific integrated circuits (ASIC) include components (i.e. gates, processors, repeaters) that operate at different frequencies. Consequently, each of these components requires their own clock signal. In practice, these multiple clock signals are generated through the use of either a phase-locked loop (PLL) or a delay-locked loop (DLL). PLL include voltage-controlled oscillator (VCO) cells that provide signals at a specific frequency. The greater the number of signals that are to be generated by the PLL, the greater the number of VCO cells that are required to be included within the PLL. A drawback associated with having multiple VCO cells within a single device is that the corresponding PLL will take up valuable real estate on the integrated circuit board. With the trend in the electronics industry moving toward reducing the footprint of devices, taking up valuable real estate with PLL""s becomes a concern.
Another drawback associated with using PLL""s having multiple VCO cells is that the operating frequency range available to each of the PLL""s will necessarily have to be reduced. Thus, multiple PLL systems are not suitable for high frequency applications or devices. With electronic devices now operating at frequencies greater than 650 MHz, conventional multiple PLL systems are not practical.
Another consideration that becomes important when using PLL systems is that the VCO cells within each PLL requires a minimum amount of power to operate properly. Thus, the greater the numbers of VCO cells that are present in a PLL, the greater the amount of power that is being used by the PLL system. This can significantly impact the performance of a low power system. The greater the amount of power being used by the PLL, the less amount of power that is available for the remainder of the components of the system.
The aforementioned and related drawbacks associated with conventional methods of generating multiple phases from an input signal are substantially reduced or eliminated by the present invention. The present invention is directed to a system and corresponding method for generating multiple phases within a single period of an input source signal. The multiple phases generated by the system of the present invention have a cyclic property. This cyclic property of the multiple phases means that the generated phases form a cycle of increasing or decreasing phases that complete over 360 degrees of a clock cycle.
According to the present invention, the method employed to generate multiple phases from a single input source, comprises the steps of generating a plurality of output signals from an input signal, each of the plurality of output signals representing a phase-shifted version of the input signal; selecting a pair of signals from the plurality of output signals to act as clock signals, the selected pair of clock signals defining the operating region of the multiple phases; providing a pair of complementary weighted bias currents, the pair of complementary weighted bias currents used to generate the multiple phases within the operating region in response to a control signal; adjusting the pair of weighted bias currents in response to the selected pair of clock signals, the selected pair of clock signals operative to adjust the rate of change of the weighted bias currents present at an output node; and providing a plurality of signals representing the difference between the value of a first one of the adjusted weighted bias currents and a second signal.
In a preferred embodiment of the present invention, the second signal is provided by a second one of the adjusted weighted bias currents. In an alternate embodiment of the present invention, the second signal is provided by a signal having a constant frequency.
According to the present invention, the system employed to generate multiple phases within a single period of an input source signal comprises an output signal block for generating a plurality of output signals in response to an input signal, each of the output signals being a phase-shifted version of the input signal; a quadratic region selection block for selecting a pair of clock signals from the plurality of output signals, the selected pair of clock signals defining the operating timing region of the multiple phases; a weighted bias current block for providing a pair of weighted complementary bias currents, the pair of weighted complementary bias currents used to generate the multiple phases within the operating timing region in response to a control signal; and a current phase interpolator block operative to generate the multiple phases by adjusting the application of the pair of weighted complementary bias currents to an output phase node in response to the selected pair of clock signals.
The weighted bias current block which provides the pair of complementary bias currents further includes a current source, a plurality of selection transistors and a pair of output nodes, wherein one of the output nodes provides a first weighted bias current in response to the selected clock signals being applied to the plurality of selection transistors, and the second output nodes provides a second weighted bias current in response to the selected clock signals being applied to the plurality of selection transistors, the second weighted bias current having a value complementary to the value of the first weighted bias current.
An advantage provided by the present invention is that it provides the ability to generate multiple clock phases within a single clock period of a source clock without the use of a phase-locked loop.
Another advantage provided by the present invention is that it provides the ability to generate multiple clock phases within a single clock period of a source clock without the use of a delay-locked loop.
Yet another advantage provided by the present invention is that multiple clock phases can be generated from a single clock source with no restriction on input clock frequency.
A feature of the present invention is that it is straightforward to implement.
Another feature of the present invention is that it reduces the footprint required of multi-phase devices.